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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 28/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Software Interface
Table 4-3 · Bus Mode Register Bit Functions
Core10100 v4.0
28
Bit
CSR0.20
CSR0.(19..17)
CSR0.(13..8)
CSR0.7
CSR0.(6..2)
CSR0.1
CSR0.0
Symbol
DBO
TAP
PBL
BLE
DSL
BAR
SWR
Function
Descriptor byte ordering mode:
1 – Big-endian mode used for data descriptors
0 – Little-endian mode used for data descriptors
Transmit automatic polling
If TAP is written with a nonzero value, Core10100 performs an automatic transmit
descriptor polling when operating in suspended state. When the descriptor is available,
the transmit process goes into running state. When the descriptor is marked as owned by
the host, the transmit process remains suspended.
The poll is always performed at the current transmit descriptor list position. The time
Programmable burst length
Specifies the maximum number of words that can be transferred within one DMA
transaction. Values permissible are 0, 4, 8, 16 and 32. When the value 0 is written, the
bursts are limited only by the internal FIFO’s threshold levels.
The width of the single word is equal to the CSRWIDTH generic parameter; i.e., all data
transfers always use the maximum data bus width.
Note that PBL is valid only for the data buffers. The data descriptor burst length depends
on the DATAWIDTH parameter. The rule is that every descriptor field (32-bit) is
accessed with a single burst cycle. For DATAWIDTH = 32, the descriptors are accessed
with a single 32-bit word transaction; for DATAWIDTH = 16, a burst of two 16-bit
words; and for DATAWIDTH = 8, a burst of four 8-bit words.
Big/little endian
Selects the byte-ordering mode used by the data buffers.
1 – Big-endian mode used for the data buffers
0 – Little-endian mode used for the data buffers
Descriptor skip length
Specifies the number of longwords between two consecutive descriptors in a ring
structure.
Bus arbitration scheme
1 – Transmit and receive processes have equal priority to access the bus.
0 – Intelligent arbitration, where the receive process has priority over the transmit process
Software reset
Setting this bit resets all internal flip-flops.
The processor should write a '1' to this bit and then wait until a read returns a '0',
indicating that the reset has completed. This bit will remain set for several clock cycles.
v4.0
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