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参数资料
| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 71/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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6
Testbench Operation and Modification
User Testbench (Core10100)
An example user testbench is included with the Obfuscated and RTL releases of Core10100. The Obfuscated and RTL
releases provide the precompiled Model Sim model, as well as the source code for the user testbench, to ease the process
of integrating the Core10100 macro into a design and verifying it. A block diagram of the example user design and
Behavioral
Behavioral
Shared RAM
μController
CSR and DMA
Core10100
User Testbench
μController
CSR and DMA
Shared RAM
Interface
CHIPMAC
MII
Simulated
Connection
Interface
MII CHIPMAC
umac1:chipmac
umac2:chipmac
Figure 6-1 · Core10100 User Testbench
The user testbench includes a simple example design that serves as a reference for users who want to implement their
own designs. RTL source code for the user testbench shown in Figure 6-1 is included in the source directory for the
Obfuscated and RTL releases of Core10100.
The testbench for the example user design implements a subset of the functionality tested in the verification testbench,
described in the previous chapter. Conceptually, as shown in Figure 6-1 , two instantiations of the Core10100 core are
connected via simulated connections in the user testbench. Example transmit and receive between the two Core10100
units is demonstrated by the user testbench so you can gain a basic understanding of how to use the core.
The source code for the user testbench contains the same example wrapper, CHIPMAC, used in the verification
testbench. For details on the support routines (tasks for Verilog testbenches; functions and procedures for VHDL
The user testbench consists of two cores: umac1 and umac2. In the example, umac1 transmits a 64-byte frame to umac2.
To do so, the user testbench exercises the following steps:
For umac1:
1.
2.
3.
4.
5.
6.
7.
Write several CSR registers to set up the operation mode.
Write two transmit descriptors into shared RAM (uram1).
Write the 64-byte data into shared RAM (uram1). The data consists of a sequence: 0, 1, 2, …, 63.
Turn on transmission.
Wait for the transmit interrupt.
Read the status register CSR5.
Clear the interrupt flags.
v4.0
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相关代理商/技术参数 |
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|---|---|
| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE12X4 | 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER |
| CORE1553BBC-AN | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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