参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 7/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Core10100 v4.0
Supported Device Families
Supported Device Families
IGLOO?
IGLOOe
ProASIC3
ProASIC3E
ProASIC?3L
Fusion
ProASIC PLUS ?
Axcelerator?
RTAX-S
Core Versions
This handbook applies to Core10100 and Core10100_AHB v4.0. The release notes provided with the core list known
discrepancies between this handbook and the core release associated with the release notes.
Supported Interfaces
Core10100 is available with the following interfaces:
? Core10100—synchronous CPU and memory interfaces (legacy interface)
? Core10100_AHBAPB—APB slave CPU interface and AHB master memory interface
Actel recommends that new designs using the SmartDesign environment use the Core10100_AHBAPB version of the
core. Core10100 is provided for backwards compliance to previous versions of Core10100.
The above interfaces are described in “Interface Descriptions” on page 19 .
Device Utilization and Performance
Core10100 can be implemented in the following Actel FPGA devices. Table 1 through Table 6 on page 9 provide the
typical utilization and performance data for the core implemented in these devices.
Table 1 · Core10100 Device Utilization and Performance for an 8-Bit Datapath
Family
Cells or Tiles
Combinatorial Sequential
Total
RAM
Utilization
Device Total
Performance
(MHz)
IGLOO?/e
4,330
1,918
6,248
14
AGLE600
45%
30
ProASIC?3
ProASIC3E
4,173
1,923
6,096
14
A3P6000
44%
49
ProASIC3L
Fusion
ProASIC PLUS ?
Axcelerator?
RTAX-S
4,215
5,547
3,087
3,055
1,918
1,958
2,207
2,014
6,133
7,505
5,114
5,069
14
29
13
13
AFS600
APA600
AX1000
RTAX1000S
44%
35%
28%
28%
56
27
73
57
v4.0
7
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