- 您现在的位置：买卖IC网 > PDF目录16069 > CORE10/100-RM (Microsemi SoC)IP CORE10/100 ETHERNET MAC PDF资料下载
参数资料
| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 54/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Software Interface
Core10100 v4.0
Receive Process
The receive process can operate in one of three modes: running, stopped, or suspended. After a software or hardware
reset, or after a stop receive command, the receive process is in the stopped state. The receive process can leave a stopped
state only after a start receive command.
In the running state, the receiver performs descriptor/buffer processing. In the running state, the receiver fetches from
the receive descriptor list. It performs this fetch regardless of whether there is any frame on the link. When there is no
frame pending, the receive process reads the descriptor and simply waits for the frames. When a valid frame is
recognized, the receive process starts to fill the memory buffers pointed to by the current descriptor. When the frame
ends, or when the memory buffers are completely filled, the current frame descriptor is closed (ownership bit cleared).
Immediately, the next descriptor on the list is fetched in the same manner, and so on.
When operating in a suspended or stopped state, the receive process retains the position of the next descriptor (the
address of the descriptor following the last descriptor that was closed). After entering a running state, the retained
position is used for the next descriptor fetch. The only exception is when the host writes the receive descriptor base
address register (CSR3). In that case, the descriptor address is reset and the fetch is pointed to the first position in the
list. Before writing to CSR3, the MAC must be in a stopped state.
When operating in a stopped state, the rps output is HIGH. This output allows for switching the receive clock clkr off
externally. When both the rps and tps outputs are HIGH, all clocks except clkcsr can be externally switched off.
The receive process runs until one of the following events occurs:
? A hardware or software reset is issued by the host. A software reset can be performed by setting the CSR0.0 (SWR)
bit. After reset, all internal registers return to their default states. The current descriptor's position in the receive
descriptor list is lost.
? A stop receive command is issued by the host. This can be performed by writing 0 to the CSR6.1 (SR) bit. The current
descriptor's position is retained.
? The descriptor owned by the host is found by Core10100 during the descriptor fetch. The current descriptor's position
is retained.
Leaving a suspended state is possible in one of the following situations:
? A receive poll command is issued by the host. This can be performed by writing CSR2 with a nonzero value.
? A new frame is detected by Core10100 on a receive link.
? A stop receive command is issued by the host. This can be performed by writing 0 to the CSR6.1 (SR) bit. The current
descriptor's position is retained.
The receive state machine goes into stopped state after the current frame is done if a STOP RECEIVE command is
given. It does not go in to a stopped state immediately.
54
v4.0
相关PDF资料 |
PDF描述 |
|---|---|
| M3CMK-2040K | IDC CABLE - MKC20K/MC20F/MCG20K |
| M3AMK-2040K | IDC CABLE - MSC20K/MC20F/MCG20K |
| M3UUK-4020K | IDC CABLE - MKS40K/MC40F/MKS40K |
| BQ26221PWG4 | IC BATTERY MONITOR HP 8-TSSOP |
| MAX6328UR29+T | IC MPU/RESET CIRC 2.93V SOT23-3 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE12X4 | 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER |
| CORE1553BBC-AN | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
发布紧急采购，3分钟左右您将得到回复。