参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 22/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Interface Descriptions
CSR Interface Signals
Table 3-3 lists the signals included on the Core10100 core.
Table 3-3 · Core10100 Signals
Core10100 v4.0
Name
Type
Polarity
Description
Control and Status Register Interface
CLKCSR
CSRREQ
CSRRW
In
In
In
Rise
HIGH
HIGH
CSR clock
This signal is set by a host to request a data transfer on the CSR interface. It can be a read or
a write request, depending on the value of the CSRRW signal.
This signal indicates the type of request on the CSR interface. Setting CSRRW indicates a
read operation, and clearing it indicates a write operation.
This signal is the data byte enable to indicate which byte lanes of CSRDATAI or
CSRBE
In
CSRWIDTH/8
CSRDATAO are the valid data bytes. Each bit of the CSRBE controls a single byte lane.
All CSRBE signal combinations are allowed.
CSRDATAI
In
CSRWIDTH
The write data is provided by the system on the CSRDATAI inputs during the write
request.
The CSRADDR receives the address of an individual CSR data transaction.
The meaning of CSRADDR depends on the CSRWIDTH parameter.
For CSRWIDTH = 32 (32-bit interface), only the CSRADDR bits from 6 down to 2 are
CSRADDR
In
8
significant. The addresses are longword-aligned (32-bit) in this mode.
For CSRWIDTH = 16 (16-bit interface), the CSRADDR bits from 6 down to 1 are
significant. The addresses are word-aligned (16-bit) in this mode.
For CSRWIDTH = 8 (8-bit interface), all bits of CSRADDR are significant. The addresses
are byte-aligned (8-bit) in this mode.
The CSRACK signal indicates either that valid data is present on the CSRDATAO outputs
CSRACK
Out
HIGH
during a read request or that the CSRDATAI inputs have been sampled during a write
request. The current version of Core10100 has the CSRACK signal statically tied to logic
1—Core10100 responds to reads and writes immediately.
CSRDATAO
Out
CSRWIDTH
The CSRDATAO signal provides the read data in response to a read request.
Data Interface
CLKDMA
In
Rise
Data clock
The DATAACK input is an acknowledge signal supplied by the host in response to the
MAC’s request. In the case of a read operation, DATAACK indicates valid data is on the
DATAI input. The DATAI input must be stable while DATAACK is set. In the case of a
DATAACK
In
HIGH
write operation, setting DATAACK indicates that the host is ready to fetch the data
supplied by Core10100 on the DATAO output. Regardless of the current transaction type
(write or read), a data transfer occurs on every rising edge of CLKDMA on which both
DATAREQ and DATAACK are set. The DATAACK signal can be asserted or
deasserted at any clock cycle, even in the middle of a burst transfer.
DATAI
22
In
DATAWIDTH
The read data must be provided on the DATAI input by the system in response to a read
request.
v4.0
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