参数资料
型号: CORE10/100-RM
厂商: Microsemi SoC
文件页数: 88/106页
文件大小: 0K
描述: IP CORE10/100 ETHERNET MAC
标准包装: 1
系列: *
Transmit and Receive Functional Timing Examples
Core10100 Enters Transmit Process
The block CSR performs this operation .
Core10100 v4.0
1.
2.
Host sets the CSR register CSR6.13 ST to start transmit.
The tps signal goes LOW after one CLKCSR cycle, which indicates that Core10100 enters the transmit process.
CLKCSR
TPS
CSRREQ
CSRRW
CSRACK
CSRBE[3:0]
(1)
(2)
CSRDATAI[31:0]
CSRADDR[7:0]
CSR6.13ST
30
Figure B-2 · Enters Transmit Process
Core10100 Starts to Request Transmit Descriptors
Figure B-3 illustrates operations between TPS going LOW and a transmit descriptor start.
1.
2.
Host sends the transmit start command.
Core10100 starts to fetch the first descriptor.
Note: t0 = 4 × CLKDMA period + 3 × CLKCSR period + z.
Where z is 2 × CLKDMA period if CLKDMA period is greater than CLKCSR period, or z is 2 × CLKCSR
period if CLKCSR period is greater than CLKDMA period. Delay z is the result of handshaking between CSR
clock domain and other domains in the design.
(1)
CLKDMA
CLKCSR
TPS
DATAACK
DATAREQ
DATARW
DATAEOB
DATAI[31:0] 80000000
DATAADDR[31:0] FFFFFFFF
t 0
(2)
600007FF
00003004
DATAO[31:0] 40000200
Figure B-3 · Core10100 Starts Transmit Descriptor Requests
88
v4.0
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