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| 型号： | CORE10/100-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 41/106页 |
| 文件大小： | 0K |
| 描述： | IP CORE10/100 ETHERNET MAC |
| 标准包装： | 1 |
| 系列： | * |
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Core10100 v4.0
Frame Data and Descriptors
Table 4-26 · General-Purpose Timer and Interrupt Mitigation Control Bit Functions (continued)
Bit
CSR11.(23..20)
CSR11.(19..17)
CSR11.16
CSR11.(15..0)
Symbol
RT
NRP
CON
TIM
Function
Receive timer
Controls the maximum time that must elapse between the end of a receive operation
and the setting of the CSR5.RI (receive interrupt) bit.
This time is equal to RT × CS.
The receive timer is enabled when written with a nonzero value. After each frame
reception, the timer starts to count down if it has not already started. It is reloaded
after every received frame.
Writing 0 to this field disables the timer effect on the receive interrupt mitigation
mechanism.
Reading this field gives the actual count value of the timer.
Number of receive packets
Controls the maximum number of received frames before setting the CSR5.RI (receive
interrupt) bit.
The receive counter is enabled when written with a nonzero value. It is decremented
after every received frame. It is reloaded after setting the CSR5.RI bit.
Writing 0 to this field disables the timer effect on the receive interrupt mitigation
mechanism.
Reading this field gives the actual count value of the counter.
Continuous mode
1 – General-purpose timer works in continuous mode
0 – General-purpose timer works in one-shot mode
This bit must always be written before the timer value is written.
Timer value
Contains the number of iterations of the general-purpose timer. Each iteration
duration is as follows:
MII 100 Mbps mode – 81.92 μs
MII 10 Mbps mode – 819.2 μs
Frame Data and Descriptors
Descriptor / Data Buffer Architecture Overview
A data exchange between the host and Core10100 is performed via the descriptor lists and data buffers, which reside in
the system shared RAM. The buffers hold the host data to be transmitted or received by Core10100. The descriptors act
as pointers to these buffers. Each descriptor list should be constructed by the host in a shared memory area and can be of
an arbitrary size. There is a separate list of descriptors for both the transmit and receive processes.
The position of the first descriptor in the descriptor list is described by CSR3 for the receive list and by CSR4 for the
transmit list. The descriptors can be arranged in either a chained or a ring structure. In a chained structure, every
descriptor contains a pointer to the next descriptor in the list. In a ring structure, the address of the next descriptor is
determined by CSR0.(6..2) (DSL—descriptor skip length). Every descriptor can point to up to two data buffers. When
using descriptor chaining, the address of the second buffer is used as a pointer to the next descriptor; thus, only one
buffer is available. A frame can occupy one or more data descriptors and buffers, but one descriptor cannot exceed a
v4.0
41
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE10GMAC-OM | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE10GMAC-OMFL | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| CORE12X4 | 制造商:Bogen Communications 功能描述:12 X 4 MATRIX CONTROLLER |
| CORE1553BBC-AN | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE1553BBC-AR | 功能描述:IP MODULE CORE1553 BUS CTLR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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