参数资料
| 型号： | IP-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 108/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 初始许可证 |
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6–8
Chapter 6: Testbench
Transmitter Testbench Description
When an error is asserted on the Atlantic interface with a valid EOP, and an end of
packet abort message is sent to the SPI-4.2 interface, it is not counted as an error in the
data and does not cause the testbench to fail.
The packet tasks for each port are called in parallel via a fork or join statement.
Arbitration is handled in the data generator module and varies for each buffer mode.
■
■
For individual buffers variations, the packets can be written in parallel.
For shared buffer with embedded addressing variations, the arbiter selects each
port in a round-robin fashion, switching to the next port at a fixed interval.
The packets have lengths defined in the top-level testbench and follow the format in
Table 6–6 .
Table 6–6. Packet Format
Packet Byte
Header byte
Format
{0,0,len[5:1],ext}
Description
Contains info about the packet. len is the length of the packet if the
length can be encoded in six bits. If the length is beyond 32 bits, ext is
set to indicate that the next byte in the packet contains the length
information.
Extra length byte {size[16:0]}
If ext is 1, the extended expected packet size shows the length of the
packet including the header ( size > 16 bytes) (optional).
Number byte
Payload bytes
{N[7:0] ^ port_num}
{N++^ port_num}
Packet number ( packet number begins at 'h01 and is incremented by
one for each packet) XOR ed with the port number.
The following bytes in the packet are incremented by one and XOR ed with
the port number.
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the POS-PHY Level 4 packet receiver (packet analyzer
module) has not detected any errors in the received packets. If no error has been
detected, and all packets have been received, the testbench issues a message stating
that the simulation was successful.
If an error has been detected, a message states that the testbench has failed. If not all
packets have been detected, a message states that the testbench is incomplete. The
tb.exp_chk_cnt variable determines the number of checks done to ensure
completeness of the testbench. For each port tested, one completeness check is done.
In addition, a preliminary check is done to make sure synchronization is complete,
and a final check is done for the conclusion of the testbench.
Optionally, the testbench can test backpressure on the SPI-4.2 interface. When the
backpressure variable is defined, backpressure is generated on one or more ports, by
first setting the status for the appropriate ports to satisfied. This action informs the
POS-PHY Level 4 transmitter MegaCore function to not send data to those ports
(specific reaction to backpressure depends on the variation selected). The data
generator continues to write to the buffers until the Atlantic aN_arxdav or aN_atxdav
signal goes high, indicating that the buffer is nearly full. The testbench then turns the
status for the satisfied ports back to starving or hungry. The POS-PHY Level 4
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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| IPPS054193X | 功能描述:保险丝 800A 1000V 3GKN/75 RoHS:否 制造商:Littelfuse 产品:Surface Mount Fuses 电流额定值:0.5 A 电压额定值:600 V 保险丝类型:Fast Acting 保险丝大小/组:Nano 尺寸:12.1 mm L x 4.5 mm W 安装风格: 端接类型:SMD/SMT 系列:485 |
| IP-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEMAC | 功能描述:开发软件 100G Ethernet Mac MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| IPR-100GEPHY | 功能描述:开发软件 100G Ethernet Phy MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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