参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 59/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
Chapter 4: Functional Description—Receiver
4–19
Error Flagging and Handling
The DIP-4 out-of-service status signal does not affect the data portion of the receiver.
However, it does affect the status channel portion, causing framing to be sent to the
adjacent device.
When reset, the stat_rd_dip4_oos flag is asserted (high). It remains asserted until the
reset is deasserted and a good_level number of consecutive control words that do not
contain DIP-4 errors are received.
Figure 4–8 shows an example of the DIP-4 counter, where the receiver is in service
state and bad threshold is 3.
Figure 4–8. DIP-4 Counter
SPI-4.2 Bus
Internal Parallel
Bus (Four-Lane)
(Note 1)
Bad DIP-4 Counter
0
1
2
2
0
0
0
Resets
Counter
Increments by 1
Increments by 1
Unchanged
Resets
Counter (1)
Resets
Resets
Counter
Counter
Non-control word (payload)
Control word witih good DIP-4
Control word with bad DIP-4
Notes to Figure 4–8 :
(1) Receiving a good and a bad DIP-4 in the same parallel cycle resets the counter (does not increment it), so that OOS
does not trigger.
f For further information on the DIP-4, refer to the System Packet Interface Level 4 (SPI-4)
Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices , available
Atlantic Interface Error Detection and Handling
When the Atlantic error checking parameter is turned on, a filtering block—the
Atlantic FIFO buffer error checker—is instantiated at the write side of the FIFO buffer
to ensure that the MegaCore function does not pass errored packets.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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