参数资料
| 型号： | IP-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 69/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description—Receiver
Avalon-MM Interface Register Map
Table 4–11. Data Path Control and Status
4–29
Signal
stat_rd_rdat_sync
Direction
Output
Clock Domain
Description
Main receiver data path sync output signal. Combination of
DPA, channel aligner sync, and DIP-4 status.
Indicates that the receiver has detected a training pattern.
stat_rd_tp_flag
stat_rd_rsv_cw
ctl_rd_dip4_good_
threshold[3:0]
ctl_rd_dip4_bad_
threshold[3:0]
stat_rd_dip4_oos
err_rd_dip4
err_rd_pr
err_rd_tp
err_rd_sob
err_rd_sop8
err_rd_abuf_oflw
ctl_rd_abuf_flush
err_rd_eightn
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Input
Output
rdint_clk
This signal is for debug purposes only. It does not indicate
that the data path is deskewed.
Indicates that the receiver has detected a reserved control
word. This signal is provided for information purposes only.
Number of consecutive correct DIP-4s to clear
stat_rd_dip4_oos . Only change at reset.
Number of consecutive DIP-4 errors to set
stat_rd_dip4_oos . Only change at reset.
Receiver’s out-of-service flag. When asserted, the MegaCore
function is still passing data, but is receiving DIP-4 errors
above a threshold.
Each clock cycle asserted indicates that one or more
(depending on the data path width parameter) calculated
DIP-4 values did not match the received DIP-4 values.
Indicates that the receiver has detected a miscellaneous
protocol error. These errors correspond to invalid state
transitions in the data path state machine.
Indicates that the receiver has detected an error in the
training pattern.
Indicates that the receiver has detected a data burst that
does not start on a payload control word.
SOP violation. Two SOPs occurred less than eight rdat
cycles apart.
Indicates that an internal buffer has overflowed and data has
been lost.
Flushes an internal buffer. While asserted, no data is written
to the Atlantic buffer(s). Data continues to be lost until
deasserted. The ctl_rd_abuf_flush signal must be
asserted for one rdint_clk cycle only, and any subsequent
assertion has to be done after minimum of approximately 20
cycles, because some ABUF internal signals are sent from
one clock domain to another.
Indicates that the receiver has detected a burst that was not
a multiple of 16 bytes.
err_ry_paddr
err_rd_eop_abort
err_rd_pad_byte_
non_zero
Output
Output
Output
rdint_clk
Invalid address received.
Indicates that the receiver has detected an EOP Abort.
Indicates that the receiver has detected an odd-sized burst
(in bytes), and the invalid pad byte was not zero.
Avalon-MM Interface Register Map
Table 4–12 lists the Avalon-MM interface registers.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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