参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 14/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
1–8
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–8. Performance—Individual Buffers Mode—Stratix III Device
Parameters
Data Flow
Direction
Receiver
Transmitter (2)
Data Path
Width (bits)
32
64
128
32
64
32
64
128
32
64
128
32
64
Number of
Ports
4
4
4
10
10
1
1
1
4
4
4
10
10
ALUTs
1,915
2,384
3,555
3,865
4,575
1,126
1,312
1,701
2,452
2,709
3,462
5,071
5,678
Logic
Registers
2,042
2,827
4,242
3,726
4,626
1,131
1,775
2,238
2,201
2,951
3,738
4,189
5,213
Memory Blocks
(M9K)
36
37
71
84
85
10
10
18
34
34
66
82
82
clk (1)
f MAX (MHz)
139
253
149
126
230
130
193
146
134
179
125
128
156
Notes to Table 1–8 :
(1) Receiver variations mostly use rxsys_clk ; transmitter variations use tdint_clk .
(2) These values are for variations that use the lite transmitter feature (refer to page 5–5 ).
Table 1–9. Performance—Individual Buffers Mode—Stratix IV Devices
Data Flow
Direction
Parameters
Data Path
Width (bits)
Number of
Ports
ALUTs
Logic
Registers
Memory
Blocks
(M9K)
clk
f MAX (MHz)
EP4SGX70 EP4SGX230
DF29C3
DF29C3ES
32
64
4
4
2,245
2,514
2,427
2,800
21
40
182
270
159
268
Receiver
Transmitter
128
32
64
32
64
128
32
64
128
32
64
4
10
10
1
1
1
4
4
4
10
10
3,833
4,070
4,823
1,155
1,309
1,710
2,563
2,726
3,430
5,210
5,733
4,160
4,529
4,830
1,213
1,784
2,245
2,524
2,997
3,778
4,789
5,188
78
45
88
6
10
18
18
34
66
42
82
165
140
255
165
245
177
130
183
166
120
153
149
144
254
176
182
171
151
212
153
118
213
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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