参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 122/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
D–2
Appendix D: Board Design
Design for Testability
Probe Points
Altera recommends that you make some of the POS-PHY Level 4 MegaCore ? function
pins and status signals available for probing using test points or connectors for logic
analyzers. Good debug connectors take little space on a PCB and have a minimal
effect on signal integrity (for example, Samtec ASP65067-01 connectors).
Receiver MegaCore Functions
The following signals connected to the POS-PHY Level 4 receiver MegaCore functions
should be made available for debugging:
SPI-4.2 data interface signals:
rdat[15:0]
rctl
rdclk
SPI-4.2 status interface signals:
rstat[1:0]
rsclk
Other useful debug signals:
FPGA reset
stat_rd_dpa_locked
stat_rd_dpa_lvds_locked
err_rd_dip4
err_ry_msopN
err_ry_meopN
rdint_clk
aN_arxerr
aN_arxeop
aN_arxclk
1
In addition to these receiver signals, it may be useful to provide test points for similar
debug and status signals from the adjacent device.
Transmitter MegaCore Functions
The following signals connected to the POS-PHY Level 4 transmitter MegaCore
functions should be made available for debugging:
SPI-4.2 Data Interface
tdat[15:0]
tctl
tdclk
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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