参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 99/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
Chapter 5: Functional Description—Transmitter
Latency Information
Table 5–11 lists the latency numbers for transmitter variations.
Table 5–11. Transmitter Latency
5–27
MegaCore Function
128-bit shared buffer with embedded addressing
128-bit individual buffers
64-bit shared buffer with embedded addressing
64-bit individual buffers
32-bit shared buffer with embedded addressing
32-bit individual buffers
Data latency:
Data Latency
(Bytes on SPI-4.2 Interface)
160
160
128
128
64
64
Status Receive Latency
(Bytes on SPI-4.2 Interface)
256
256
256
256
256
256
The values in Table 5–11 do not include the latency through the user-side buffers.
The external support in the shared buffer with embedded addressing mode adds
8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.
Status latency:
The values do not include the time spent waiting for a complete error-free status
message. The resultant value also reflects the status channel mode—either
optimistic or pessimistic.
Turning on Lite Transmitter adds up to 32 bytes for 128-bit data path widths, or
up to 16 bytes for 64-bit data path widths.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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