参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 117/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
B. Sharing PLLs for Multicore Designs
This appendix explains how to share a PLL between one receiver and one transmitter
POS-PHY 4 MegaCore functions and between two transmitter cores.
Figure B–1 shows how to connect the reset and the rdclk and trefclk signals when
you share a PLL between a receiver and transmitter core.
1
Even though Figure B–1 shows two PLLs, the Quartus II software optimizes the PLL
instance as if it is one PLL.
Figure B–1. Connect rdclk and trefclk Signals
rdclk
Separate PLLs
Top-Le v el Entity
< variation name >. v
< variation name >_rx_core. v
altl v ds Megafunction
rdclk
Shared PLL
Top-Le v el Entity
< variation name >. v
< variation name >_rx_core. v
altl v ds Megafunction
reset
PLL
reset
PLL
reset
< variation name >. v
< variation name >_tx_core. v
altl v ds Megafunction
reset
< variation name >. v
< variation name >_tx_core. v
altl v ds Megafunction
trefclk
tdclk
PLL
trefclk
tdclk
PLL
To share the PLL, follow these steps:
1
The LVDS data rates must be the same for each core.
1. Create a new Quartus II project, but call the project name and the top-level entity
names different names.
2. Create your receiver core.
3. Create your transmitter core.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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