参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 139/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
Appendix G: Conversion from v2.2.x
G–5
Transmitter Signals
Table G–2 shows the new 2.4.x and v2.3.x transmitter signal names as they exist in the
MegaWizard Plug-In top-level file, their equivalent v2.2.x signal names (if applicable),
and notes explaining the changes.
Table G–2. Transmitter Signal Changes (Part 1 of 3)
Version 2.4.x and 2.3.x Signal
Name
tdclk
tctl
tdat[15:0]
tsclk
tstat[1:0]
tsreset_n
trefclk
stat_tx_pll_locked
tdint_clk
tdint_reset_n
txsys_clk
txsys_reset_n
txreset_n
txinfo_aot[12:0]
aN_atxclk
aN_atxreset_n
aN_atxdav
aN_atxena
aN_atxdat
aN_atxsop
aN_atxeop
aN_atxmty
aN_atxerr
aN_atxadr
Version 2.2.x Signal Name
tdclk
tctl
tdat[15:0]
tsclk
tstat[1:0]
trefclk
tx_coreclock
txreset_n
txinfo_aot[15:0]
aN_atxclk
aN_atxreset_n
aN_atxdav
aN_atxena
aN_atxdat
aN_atxsop
aN_atxeop
aN_atxmty
aN_atxerr
aN_atxadr
Notes
No change.
New. Tied high in the IP Toolbench top-level
for usage.
No change.
New signal indicating PLL lock.
Derived from trefclk . Signals synchronous
to this clock are infixed by _td_ .
New. Tied high in the IP Toolbench top-level
for usage.
Signals synchronous to this clock are infixed
by _ty_ .
New. Tied high in the IP Toolbench top-level
for usage.
No change. Resets all domains.
Change in port width.
No change
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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