参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 12/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
1–6
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–4. Performance—Shared Buffer With Embedded Addressing Mode—Cyclone III Device (Part 2 of 2)
Parameters
Memory Blocks
Data Flow Direction
Transmitter (2)
Data Path Width
(bits)
32
32
Number of Ports
4
10
LEs
1,405
1,489
M9K
9
10
clk (1)
f MAX (MHz)
140
146
Notes to Table 1–4 :
(1) Receiver variations mostly use rxsys_clk ; transmitter variations use tdint_clk .
(2) These values are for variations that use the lite transmitter feature (refer to page 5–5 ).
Table 1–5. Performance—Shared Buffer With Embedded Addressing Mode—Stratix III Device
Parameters
Memory Blocks
Data Flow
Direction
Receiver
Transmitter (2)
Data Path
Width (bits)
32
64
128
32
64
128
32
64
128
32
64
128
32
64
128
Number of
Ports
1
1
1
4
4
4
10
10
10
4
4
4
10
10
10
ALUTs
855
1,287
2,176
864
1,301
2,186
857
1,319
2,760
875
944
1,177
901
1,042
1,896
Logic
Registers
1,089
1,809
3,017
1,085
1,846
3,032
1,186
2,082
4,521
850
1,326
1,456
939
1,579
2,931
M9K
10
17
23
10
17
23
11
14
8
9
13
17
10
10
2
clk (1)
f MAX (MHz)
193
266
138
172
275
158
203
260
151
162
186
151
155
231
148
Notes to Table 1–5 :
(1) Receiver variations mostly use rxsys_clk ; transmitter variations use tdint_clk .
(2) These values are for variations that use the lite transmitter feature (refer to page 5–5 ).
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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