参数资料
| 型号： | IP-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 44/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
4–4
Chapter 4: Functional Description—Receiver
Block Description
Figure 4–2. DPA and Channel Aligner Block Diagram
Notes to Figure 4–2 :
(1) The width of the data path for the data_out , data_out_algn , and data:2 signals depends on the deserialization factor.
(2) Exists only for Stratix GX devices, if the internal data path width is 64 bits.
(3) The stat_rd_dpa_lvds_locked signal does not exist in the altlvds block for Stratix GX devices. It is tied to a logic 1 inside the receiver
MegaCore function.
ALTLVDS_RX Megafunction
The ALTLVDS_RX megafunction always performs deserialization on the input rdat
and rctl high-speed LVDS signals, and divides the DDR rdclk to produce a slower
rdint_clk .
When DPA is enabled in the POS-PHY Level 4 MegaCore function, the ALTLVDS_RX
megafunction has two other features enabled: DPA and bit slip. DPA with respect to
ALTLVDS has a different meaning than DPA with respect to the POS-PHY Level 4
MegaCore function. After DPA resets, the ALTLVDS DPA feature tolerates only a
small amount of change to the channel-to-channel skew, which compensates for the
very small amounts of change in channel-to-channel skew that may occur due to
voltage and temperature shifts during system operation. A change in channel-channel
skew that is greater than the bit-time tolerance causes one or more of the internal
deskew FIFO buffers to underflow or overflow, which the POS-PHY Level 4
MegaCore function detects only as DIP-4 errors. You must use the DIP-4 thresholds
and stat_rd_dip4_oos to trigger the DPA reset by asserting
ctl_rd_dpa_force_unlock .
The stat_rd_dpa_lvds_locked signal indicates when the DPA cannot stay locked
either because of a lack of transitions on the channel, or because of rapid changes in
skew. The DPA run length is 6,400 UI for Stratix III, Stratix II, and Stratix GX devices.
If the traffic on the SPI-4.2 interface is very sparse, periodic training patterns may be
required.
To compensate for large amounts of static channel-to-channel skew, the POS-PHY
Level 4 MegaCore function channel aligner state machine uses the bit slip feature (the
channel align or data realignment) of the ALTLVDS_RX megafunction.
The POS-PHY Level 4 MegaCore function automatically configures and includes the
ALTLVDS_RX megafunction.
Channel Aligner
The DPA feature of the ALTLVDS_RX megafunction provides parallel data sampled
correctly and aligned to a single clock. As it does not use a data pattern, it cannot
compensate for more than one bit time of channel-to-channel skew which may exist
due to trace length mismatches.
The channel aligner sub-block uses the SPI-4.2 training pattern to align the parallel
data. Alignment is done once at start-up, and then only when requested by asserting
the ctl_rd_dpa_force_unlock signal. The channel aligner state machine begins the
alignment process once the ctl_rd_dpa_force_unlock signal is deasserted and the
altlvds_rx megafunction asserts the stat_rd_dpa_lvds_locked signal (high). It then
pulses the bits of the align[16:0] signal channel by channel until all channels are
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RIOPHY | IP RAPID I/O |
| IP-RLDRAMII | IP RLDRAM II CONTROLLER |
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPPS054193X | 功能描述:保险丝 800A 1000V 3GKN/75 RoHS:否 制造商:Littelfuse 产品:Surface Mount Fuses 电流额定值:0.5 A 电压额定值:600 V 保险丝类型:Fast Acting 保险丝大小/组:Nano 尺寸:12.1 mm L x 4.5 mm W 安装风格: 端接类型:SMD/SMT 系列:485 |
| IP-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEMAC | 功能描述:开发软件 100G Ethernet Mac MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEMACPHY | 功能描述:开发软件 100 Gb Ethernet MAC PHY MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEPHY | 功能描述:开发软件 100G Ethernet Phy MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。