参数资料
| 型号： | IP-POSPHY4 |
| 厂商： | Altera |
| 文件页数： | 18/144页 |
| 文件大小： | 0K |
| 描述： | IP POS-PHY L4 |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | POS-PHY 4 级接口，链路层/物理层 |
| 许可证： | 初始许可证 |
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2–2
Chapter 2: Getting Started
Specify Parameters
5. Click Step 2: Set Up Simulation in IP Toolbench.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
c You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
creates a nonfunctional design.
6. Turn on Generate Simulation Model .
7. Choose the language in the Language list.
8. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist .
9. Click OK .
10. Click Step 3: Generate in IP Toolbench.
Table 2–1 describes the generated files and other files that may be in your project
directory. The names and types of files specified in the IP Toolbench report vary
based on whether you created your design with VHDL or Verilog HDL
1
If you want to change your project from a receiver to a transmitter, delete all
the HDL files before you regenerate the MegaCore function.
Table 2–1. Generated Files (Part 1 of 2)
File
< variation name > _atlfifo_concat.v
< variation name > _dpa_concat.v
< variation
name > _pl4_rx_core_constraints.tcl
< variation name > _refresh_model.tcl
< variation name > _run_modelsim.tcl
< variation name > _rx_data_proc.ocp
< variation name > _rx_modules.v
< variation
name > _rx_data_phy_altlvds.v
< variation name > _rx_core.v
< variation name > _syn.v or
< variation name > _syn.vhd
POS-PHY Level 4 MegaCore Function User Guide
Description
An encrypted HDL file for Quartus II synthesis. This file is automatically added
to your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
Constraint settings file for Quartus II synthesis. Use this file to specify
constraints required to achieve performance requirements.
A Tcl script that regenerates the IP functional simulation model, in both Verilog
HDL ( .vo ) and VHDL ( .vho ) formats.
A Tcl script that automates the process of running the testbench with the IP
functional simulation model.
An OpenCore Plus file, for time limited or tethered hardware evaluation.
An encrypted HDL file for Quartus II synthesis. This file is automatically added
to your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
A timing and resource netlist for use in some third-party synthesis tools.
May 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-RIOPHY | IP RAPID I/O |
| IP-RLDRAMII | IP RLDRAM II CONTROLLER |
| IP-RSDEC | IP REED-SOLOMON DECODER |
| IP-SDI | IP VIDEO INTERFACE - SDI |
| IP-SDRAM/DDR2 | IP DDR2 SDRAM CONTROLLER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPPS054193X | 功能描述:保险丝 800A 1000V 3GKN/75 RoHS:否 制造商:Littelfuse 产品:Surface Mount Fuses 电流额定值:0.5 A 电压额定值:600 V 保险丝类型:Fast Acting 保险丝大小/组:Nano 尺寸:12.1 mm L x 4.5 mm W 安装风格: 端接类型:SMD/SMT 系列:485 |
| IP-QDRII/UNI | 功能描述:开发软件 QDRII SRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEMAC | 功能描述:开发软件 100G Ethernet Mac MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEMACPHY | 功能描述:开发软件 100 Gb Ethernet MAC PHY MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-100GEPHY | 功能描述:开发软件 100G Ethernet Phy MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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