参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 133/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
Appendix F: Static and Dynamic Phase Alignment
AC Timing Analysis
F–5
1
The calculations follow those in OIF2000.088.4, Appendix D Sample LVDS Timing
Budgets .
Figure F–3. Timing Analysis Model
Channel Distortion
Serializer
for
Data
Channel
Buffer Distortion
(Duty Cycle)
Buffer Distortion
(Duty Cycle)
Data Dependent Jitter
(Deterministic)
Board Effects
Channel-to-Channel
Data Sampling Window
Deserializer
Skew Relative to Clock
Serializer
Fast
PLL
for
Source
Synchronous
Clock
Random (Intrinsic)
Jitter
Reference Point A
Reference Point B
PLL
Jitter Attenuation/Pass-Through
plus Intrinsic Jitter
Clock Source
Jitter
Clock
Source
Figure F–4. Timing Diagram
Clock Placement
Internal Clock
Synchronization
Transmitter
Output Data
TCCS
TCCS/2
Receiver
Input Data
SW
f For timing information on the SPI-4 Phase 2 interface, refer to the Optical
Internetworking Forum (OFI), System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1:
OC-192 System Interface for Physical and Link Layer Devices , OIF-SPI4-02.1, October 2003.
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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