参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 82/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
5–10
Chapter 5: Functional Description—Transmitter
Clock Structure
Figure 5–4 on page 5–10 shows the multiple clock domain clocking structure for the
transmitter MegaCore function in full-rate mode.
Figure 5–4. Clock Layout Diagram (Full Rate)
tdint_clk
altl v ds Megafunction
a0_atxclk
tdat[15:0]
tctl
tdclk
SERDES
Data
Processor
Atlantic
Buffer 0
Atlantic
Interface 0
trefclk
LVDS
PLL
LVTTL
tsclk
Status
ctl_ts_statedge
Processor
txsys_clk
tstat[1:0]
LVTTL
2
Notes to Figure 5–4 :
(1) Stratix and Stratix GX devices use trefclk for tdint_clk . All other device families use the PLL output clock.
(2) The single clock mode removes the separate Atlantic clocks.
(3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.
Figure 5–5 on page 5–11 shows the clocking structure for the transmitter MegaCore
function, for 32-bit (quarter rate) SPI-4.2 mode variations. For 32-bit variations, the
ALTLVDS_TX block is replaced by an ALTDDIO_OUT block and there is no LVDS
PLL function that is clocked by trefclk .
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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