参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 13/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
Chapter 1: About This MegaCore Function
Performance and Resource Utilization
Table 1–6. Performance—Shared Buffer With Embedded Addressing Mode—Stratix IV Devices
1–7
Data Flow
Direction
Parameters
Data Path
Width (bits)
Number of
Ports
ALUTs
Logic
Registers
Memory
Blocks
(M9K)
clk
f MAX (MHz)
EP4SGX70 EP4SGX230
DF29C3
DF29C3ES
32
64
128
32
1
1
1
4
1,190
1,387
2,215
1,198
1,294
1,820
2,741
1,300
6
16
30
6
204
261
186
199
195
284
207
156
Receiver
Transmitter
64
128
32
64
128
32
64
128
32
64
128
4
4
10
10
10
4
4
4
10
10
10
1,398
2,221
1,138
1,396
2,273
1,049
1,032
1,178
1,023
1,057
1,331
1,826
2,742
1,249
1,782
2,709
1,085
1,454
1,464
1,119
1,601
1,770
16
30
7
18
33
5
9
17
5
9
17
273
195
213
281
187
192
262
175
178
260
190
273
195
163
270
160
185
232
181
163
225
166
Table 1–7. Performance—Individual Buffers Mode—Cyclone III Device
Parameters
Memory Blocks
Data Flow Direction
Receiver
Transmitter (2)
Data Path Width
(bits)
32
32
32
32
32
Number of Ports
1
4
10
4
10
LEs
3,082
5,725
1,786
3,561
7,035
M9K
36
84
10
34
82
clk (1)
f MAX (MHz)
145
130
129
110
118
Notes to Table 1–7 :
(1) Receiver variations mostly use rxsys_clk ; transmitter variations use tdint_clk .
(2) These values are for variations that use the lite transmitter feature (refer to page 5–5 ).
May 2013
Altera Corporation
POS-PHY Level 4 MegaCore Function User Guide
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