参数资料
型号: IP-POSPHY4
厂商: Altera
文件页数: 132/144页
文件大小: 0K
描述: IP POS-PHY L4
标准包装: 1
系列: *
类型: MegaCore
功能: POS-PHY 4 级接口,链路层/物理层
许可证: 初始许可证
F–4
Appendix F: Static and Dynamic Phase Alignment
AC Timing Analysis
f For more information on the use of DPA in the POS-PHY Level 4 MegaCore function,
f For more information on using dynamic phase alignment, refer to the following
documents:
Stratix II Device Handbook
AC Timing Analysis
Specifications for this interface allow two sets of timing relationships between the
sender and receiver: static and dynamic mode. In the static alignment mode, all data
obeys a common set of timing parameters (for example, set up and hold times with
respect to a sampling clock). In the dynamic alignment mode, a per-bit timing
relationship applies.
This section describes the timing analysis for various configurations and components.
These timing components are referenced to Figure F–3 on page F–5 , which shows the
timing path as related to the paths followed by the clock and data signals through the
user ’s system. Figure F–4 on page F–5 references the timing values to the clock and
data edges.
POS-PHY Level 4 MegaCore Function User Guide
May 2013 Altera Corporation
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