参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 101/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
3
Silicon Integrated Systems Corporation
Meets PC98 Requirements
Supports PCI Revision 2.1 Specification
Provides High Performance PCI Arbiter.
Supports up to 4 PCI Masters
Supports Rotating Priority Mechanism
Hidden Arbitration Scheme Minimizes Arbitration Overhead.
Supports Concurrency between CPU to Memory and PCI to PCI.
Programmable Timers Ensure Guaranteed Minimum Access Time for PCI Bus Masters, and CPU
Integrated Host-to-PCI Bridge
Supports Asynchronous PCI Clock
Translates the CPU Cycles into the PCI Bus Cycles
Zero Wait State Burst Cycles
Supports Pipeline Process in CPU-to-PCI Access
Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
Supports Memory Remapping Function for PCI master accessing Graphical Texture Range
Reassembles PCI burst data size into optimized block size for the data snooping in the host bus to
minimize interference on CPU
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
Supports Synchronous/ Asynchronous A.G.P. Clock
Supports 1X, and 2X Mode for A.G.P. 66/133 MHz 3.3V device
Translates the CPU Cycles into the A.G.P. Bus (PCI66) Cycles
Translates Sequential CPU-to-AGP Memory Write Cycles into A.G.P. Bus (PCI66) Burst Cycles
Zero Wait State Burst Cycles
Supports Pipeline Process in CPU-to-A.G.P. Access
Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
Reassembles PCI burst data size into optimized block size for the data snooping in the host bus to
minimize interference on CPU
Supports PCI-to-PCI bridge function for memory write from 33Mhz PCI bus to A.G.P. bus
Fast PCI IDE Master/Slave Controller
Supports PCI Bus Mastering
Plug and Play Compatible
Supports Scatter and Gather
Supports Dual Mode Operation - Native Mode and Compatibility Mode
Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
Supports Multiword DMA Mode 0, 1, 2
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