参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 14/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
107
Silicon Integrated Systems Corporation
3:2
R/W
Initial Latency Control
This field controls the target initial latency of the PCI66 target bridge. If SiS600 is
unable to assert TRDY# for a transaction within the target initial latency defined by
this field, SiS600 asserts STOP# to retry this cycle.
00: Disable
01: 16 PCI33 Clocks
10: 32 PCI33 Clocks
11: 48 PCI33 Clocks
1
R/W
Subsequent Latency Control
When this bit is enabled, SiS600 terminates a transaction with STOP# if it is unable
to assert TRDY# for the subsequent data transfers within 8 clocks.
0: Disable
1: Enable
0
R/W
Test Mode
This bit controls the test mode for PCI66.
0: Test mode
1: Normal mode
Register E3h
CPU to PCI66 Bridge characteristics
Default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7:3
R/W
Reserved
2
R/W
Non-Post Cycle Retry Behavior Control
When enabled, CPU-to-PCI non-post cycle being retried by PCI target will be
regenerated once, before SiS600 backs off CPU. When disabled, SiS600 will back off
CPU immediately when the current CPU-to-PCI non-post cycle is being retried.
1: Enable
0: Disable
1
R/W
Memory Burst Control
This bit enables the host bridge to generate memory burst cycles.
0: Disable
1: Enable
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