参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 19/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
112
Silicon Integrated Systems Corporation
Register 1Ah
Subordinate Bus Number (SUBUSN)
Default Value:
00h
Access:
Read/Write
This register is used to record the number of the highest numbered PCI bus that is behind A.G.P. bus.
BIT
ACCESS
DESCRIPTION
7:0
R/W
Subordinate Bus Number
Default value is 00h.
Register 1Bh
Secondary Master Latency Timer (SMLT)
Default Value:
00h
Access:
Read/Write, Read Only
This register adheres to the definition of the Latency Timer in the PCI Local Bus Specification but applies only to
A.G.P. interface.
BIT
ACCESS
DESCRIPTION
7:3
R/W
Secondary Master Latency Timer
Unit: 8 * A.G.P clock
2:0
RO
Reserved
Register 1Ch
I/O Base
Default Value:
0Fh
Access:
Read/Write, Read Only
The I/O Base register defines the bottom address of an address range that is used by SiS600 to determine when to
forward I/O transactions from CPU to A.G.P. bus.
BIT
ACCESS
DESCRIPTION
7:4
R/W
I/O Address Base A[15:12]
Bits[7:4] controls the CPU to A.G.P. I/O access. 600 forward I/O cycle initiated by
CPU to A.G.P. if the address of the cycle meets the following requirement.
IO_BASE
≤ address ≤ IO_LIMIT
3:0
RO
Reserved
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