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| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 91/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
47
Silicon Integrated Systems Corporation
data from system memory to IDE, the DMA engine will initiate PCI burst cycles to read data from memory into
FIFO until FIFO is full. The FIFO will decrease at the rate of the selected Ultra DMA mode as the IDE controller
doing data-out operation. In the best situation, the FIFO should not be empty during data-out operation otherwise
the burst data transfer on IDE will be suspended.
The Ultra-DMA mode can be enabled on a per-device basis and all three timing modes(0-2) are supported by
programming the corresponding configuration registers. For Ultra-DMA operations, the following signal lines
shall change to their new definition when IDACK# is asserted. These signals will revert back to their old
definitions right after IDACK# is de-asserted.
The following table shows the signal line difference between old definition and new definition (Ultra DMA).
Table 5.6-3 Table for Different Command Definition
Old Definition
New Definition
IIOW#
STOP#
IIOR#
HDMARDY# --- data in operation
HSTROBE --- data out operation
ICHRDY#
DSTROBE --- data in operation
DDMARDY# --- data out operation
There are three phases for an Ultra-DMA operation as defined in the protocol: Burst Initiation phase, Data
Transfer phase and Burst Termination phase. The Burst Initiation phase is always initiated by the device when it
asserts IDREQ. The SiS Chip will responds IDACK# after the base address and byte-count in the PRD table entry
is read from system memory. During Data Transfer phase, either the sender or the receiver can pause a burst to
allow for internal data processing and then resume the burst some time later. There are three situations that SiS
Chip will pause a burst:
1.
As a sender during data-out operation and the internal FIFO is empty. The burst will resume after the DMA
engine re-fill the FIFO with data from system memory.
2.
As a receiver during data-in operation and the internal FIFO is full. The burst will resume after the DMA
engine dump the data in FIFO to system memory.
3.
For a PRD table with multiple entries, the DMA engine will start the burst data transfer after base address
and byte-count of one entry are read. When the data transfer for the current entry is completed and the next
entry has not yet been read into the controller, the SiS Chip shall also initiate a pause. After the base address
and byte-count for next entry is read, the burst resumes.
The Burst Termination phase can be initiated by either the SiS Chip or the device. In normal situations, when the
data transfer has reached the byte-count as defined in the last entry of the PRD table, the SiS Chip will initiate a
burst termination by asserting STOP#. After the termination is acknowledged by the device and HSTROBE
signal return to the asserted state, the CRC will be sent on negation of IDACK#. There is an additional situations
that the SiS Chip will also initiate a burst termination:
1.
During the burst data transfer, the host(CPU) is trying to access the command/control block registers. Since
the command/control block access cycle is assigned to have higher priority than data transfer cycles, the SiS
Chip must first terminate the burst, de-asserts the IDACK# signal, generate the corresponding DA[2:0] and
CS[1:0] on IDE bus, and then complete the command/control block register access cycle. After that, the
burst can be resumed by entering the Burst Initiation phase when the device re-asserts IDREQ.
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