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| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 92/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
48
Silicon Integrated Systems Corporation
5.7.
BALL CONNECTIVITY TESTING
SiS Chip will provide a NAND chain Test Mode by TEST_PIN# signal is pull low. In order to ensure the
connections of balls to tracks of main board, SiS Chip provides a simple way to do connective measurements.
Basically, an additional 2-input-NAND gate is added into the I/O buffer cells. And, one of inputs of NAND gate
is connected to input pin of I/O buffer as test input port in test mode. To monitor the test result at test output port,
the output of the NAND gate is connected to the other input of the next NAND gate. Such that, the test result
could be propagated and it forms a NAND tree, as depicted in Figure 5.7-1. To adapt to the scheme, all output
buffers of SiS Chip are changed to bi-direction buffers to accept test signals.
5.7.1. TEST SCHEME
There are six NAND tree chains are provided by SiS Chip. Each NAND tree chain has several test-input pins and
one output pin.
The following description is an example on 4-test-input pins to explain a NAND tree chain test scheme.
First of all, logic LOW is driven into TESTIN1 pin from track on main board. If logic HIGH could be observed at
TESTOUT pin, it means that the connection of TESTIN1 pin to track is good, as shown in Figure 5.7-2. To test
TESTIN2 pin, TESTIN2 pin should be driven LOW also. And, TESTIN1 pin should be kept at logic HIGH, such
that the test result could be passed to TESTOUT pin and so on. Although SiS Chip operates at 3.3V, all input
buffers of SiS Chip are 5V-input tolerance. Hence, all test signal could go up to 5V.
5.7.2. MEASUREMENTS
During test process, this scheme requires all test inputs to be driven simultaneously. To decrease the amount of
test probes, SiS Chip divide pins into 6 branches. Meanwhile, some noise sensitive signals or analogue signals, i.e.
RTC, and power signals, are excluded. The final number of test-input probes is limited to 78 and these six NAND
trees are listed on next page.
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