参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 21/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
114
Silicon Integrated Systems Corporation
Register 20h
Non-prefetchable Memory Base Address (MBASE)
Default Value:
FFF0h
Access:
Read/Write, Read Only
The register defines the base address of a non-prefetchable memory address range that is used by SiS600 to
determine when to forward memory transactions from CPU to A.G.P. bus.
BIT
ACCESS
DESCRIPTION
15:4
R/W
Memory Address Base A[31:20]
Bits[15:4] controls the CPU to A.G.P. memory access. SiS600 forward I/O cycle
initiated by CPU to A.G.P. bus if the address of the cycle meets the following
requirement.
MBASE
≤ address ≤ MLIMIT
3:0
RO
Reserved
Register 22h
Non-prefetchable Memory Limit Address (MLIMIT)
Default Value:
0000h
Access:
Read/Write, Read Only
The register defines the top address of a non-prefetchable memory address range that is used by SiS600 to
determine when to forward memory transactions from CPU to A.G.P. bus.
BIT
ACCESS
DESCRIPTION
15:4
R/W
Memory Address Limit A[31:20].
Bits[15:4] controls the CPU to A.G.P. memory access. SiS600 forward I/O cycle
initiated by CPU to A.G.P. bus if the address of the cycle meets the following
requirement.
MBASE
≤ address ≤ MLIMIT
3:0
RO
Reserved
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