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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 112/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
4
Silicon Integrated Systems Corporation
Supports Ultra DMA/33
Two 16 Dword FIFO for PCI Burst Transfers.
Integrated Posted Write Data Buffers and Read Prefetch Data Buffers to Increase System
Performance
CPU-to-Memory Posted Write Data Buffer with 8 QW Deep, Always Sustains 0 Wait Performance on
CPU-to-Memory.
CPU-to-Memory Read Data Buffer with 8 QW Deep
CPU-to-PCI or CPU-to-AGP multi-purpose Write Data Buffer with 16QW Deep
CPU-to-PCI dedicates Posted Write Data Buffer with 4 DW Deep (cascade with multi-purpose Write
FIFO)
PCI-to-Memory Posted Write Data Buffer with 16 QW Deep, Always Streams 0 Wait performance on
PCI-to/from-Memory Access
PCI-to-Memory Read Prefetch Data Buffer with (16 QW + 4 DW) Deep
CPU-to-A.G.P. dedicates Posted Write Data Buffer with 4 DW Deep (cascade with multi-purpose
Write FIFO)
CPU-to-Memory Posted Write Data Buffer with 8 QW Deep
Request Queue With the Depth of 32
High Priority Write Data Queue with 64 QW Deep
Low Priority Write Data Queue with 64 QW Deep
High Priority Read Data Return Queue with 64 QW Deep
Low Priority Read Data Return Queue with 64 QW Deep
Concurrent execution between CPU, AGP and PCI Transactions
CPU-to- DRAM read/write and PCI-to-PCI read/write
CPU-to-DRAM read/write and PCI-to-DRAM read/write (these two types of transactions are mixed
and arranged on host bus, dispatched to DRAM sequentially)
CPU-to-DRAM read/write and AGP-to-DRAM read/write (these two types of transactions are mixed
and arranged on host bus, dispatched to DRAM sequentially)
CPU-to-DRAM read/write and AGP-to-PCI write (or PCI-to-AGP write), (these two types of
transactions are mixed and arranged on host bus, dispatched to their destination respectively)
CPU-to-PCI write (or AGP-to-PCI write) and PCI-to-DRAM write (CPU-to-PCI, AGP-to-PCI write
are temporary queued in multi-purpose FIFO if PCI-to-DRAM burst write is too long)
CPU-to-AGP write (or PCI-to-AGP write) and AGP-to-DRAM write (CPU to AGP write, PCI-to-
AGP write are temporary queued in multi-purpose FIFO if AGP-to-DRAM burst write is too long)
Supports NAND Tree for Ball Connectivity Testing
487-Balls BGA Package
3.3V CMOS Technology
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| SIS776DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:N-Channel 30 V (D-S) MOSFET with Schottky Diode |
| SIS776DN-T1-GE3 | 制造商:Vishay Siliconix 功能描述:MOSFET N-CH 30V 18.3A 1212-8 |
| SiS778DN-T1-GE3 | 功能描述:MOSFET 30 Volts 35 Amps 52 Watts RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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| SiS780DN-T1-GE3 | 功能描述:MOSFET 30 Volts 18 Amps 27.7 Watts RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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