参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 117/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
71
Silicon Integrated Systems Corporation
Register 55h
DRAM MISC Control 2
default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7
R/W
RAMW# Assertion Timing for EDO/FP Mode DRAM
This bit is only valid for EDO/FP DRAM.
0: Normal
1: Faster
6
R/W
EDO Detection Bit for BIOS
This bit is used by BIOS to detect whether the DRAM type is EDO or FP DRAM.
When set to 1, SiS600 will return BRDY# about 2
12 CPU clocks later. In such case,
BIOS can read correct data for EDO since data will still be valid on MD bus. For FP,
data will be wrong. After BIOS finishes DRAM detection procedure, this bit should
be programmed to “0”.
0: Disable
1: Enable
5
R/W
Turn Around Time Control between SDRAM Read and Write Cycles
This bit is used to control memory data bus (MD) turn around time between two
consecutive SDRAM read and write cycles. The turn around time in normal condition
should be 1T. For certain SDRAMs that will not halt the driving of MD in time, the
turn around time will be 2T to avoid contention.
0: 1T
1: 2T
4
R/W
SDRAM RAS# Precharge Time Control
When this bit is enabled, SiS600 will optimize the RAS# precharge time by
comparing the memory address of every consecutive DRAM cycles to check whether
the addresses are located at the same row or not. If the cycles are destined to the same
row, the minimum RAS# precharge time for SDRAM should be met before issuing a
row active command. However, if they are destined to the different rows, the RAS#
precharge time is met automatically, and row active command can be issued
immediately.
0: Disable
1: Enable
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