参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 6/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
100
Silicon Integrated Systems Corporation
Register 98h
Page Table Cache Invalidation Control
Default Value:
00000000h
Access:
Read/Write
This register controls the invalidation of page table cache. The invalidation can be applied to only one entry or to
all entries.
BIT
ACCESS
DESCRIPTION
31:12
R/W
Graphic Window Memory Address
Bits[31:12] define A[31:12] of a specific page of 4K A.G.P. graphic window
memory address. There is a certain GART entry to handle address translation of the
page. If the GART entry is resided in the page table cache and “1” is being written
to bit 0 of this register, it is going to be invalidated.
11:2
R/W
Reserved
1
R/W
Invalidate All
Invalidate all page table cache entries when a “1” is being written to this bit. This
bit is cleared after the invalidation is completed.
0
R/W
Invalidate Entry
Invalidate the corresponding page table cache entry specified in Bits[31:12] when a
“1” is being written to this bit. This bit will be cleared after the invalidation is
completed.
Register 9Ch ~ AFh Reserved
8.1.12. A.G.P AND 66MHZ HOST BRIDGE CONTROL REGISTERS
Register C0h
AGP Capability Identify Register(ACAPID)
Default Value:
00100002h
Access:
Read Only
BIT
ACCESS
DESCRIPTION
31:24
RO
Reserved
23:20
RO
AGP revision Major
Default value is “0001b” to indicate that SiS600 conforms to the major revision 1
of A.G.P. interface specification.
19:16
RO
AGP revision Minor
Default value is “0000b” to indicate that SiS600 conforms to the minor revision 0
of A.G.P. interface specification..
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