参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 12/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
106
Silicon Integrated Systems Corporation
1
R/W
Synchronous Mode.
This bit can only be enabled when A.G.P. clock and CPU clock are generated from
the same source and the external skew between these two clocks is less than 2ns.
0: Disable
1: Enable
0
R/W
TRDY# Delay for Data Transfer
When set to 0, TRDY# is asserted in the fastest timing for read data transfer. When
set to 1, the assertion of TRDY# for read data transfer is delayed 1 clock.
0: Minimum Delay
1: Maximum Delay
Register E1h
Reserved
Register E2h
PCI66 Target Bridge Characteristics
Default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7
R/W
Reserved
6
R/W
PCI 33/66 Memory Read Multiple Lines Control
This bit is only valid when PCI master memory read prefetch function is enabled.
(Controlled by Register 82h bits[5:4] and Register E2h bits[5:4] for PCI33 and
PCI66, respectively). When this bit is 0, one more pending memory read prefetch
cycle will be issued by SiS600 for PCI masters; when this bit is 1, two more
pending memory read prefetch cycles can be generated.
0: 1 more pending cycle
1: 2 more pending cycles
5
R/W
PCI66 Memory Read Line or Memory Read Multiple Command Prefetch
Enable
This bit enables data prefetching for Memory Read Line or Memory Read Multiple
commands.
0: Disable
1: Enable
4
R/W
PCI66 Memory Read Command Prefetch Enable
This bit enables data prefetching for Memory Read command.
0: Disable
1: Enable
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