参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 56/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
16
Silicon Integrated Systems Corporation
4.1.2. DRAM CONTROLLER
NAME
TYPE ATTR
DESCRIPTION
MD[63:0]
I/O
Memory Data Bus :
MD[63:0] contain 64-bit data between SiS600 and memory.
MA[13:0]
O
Memory Address Lines 14-2:
Memory address 14-2 are the row and column addresses for
DRAM.
CS[5:0]#/RAS[5:0]#
O
Chip Select (SDRAM)/ Row Address Strobe (EDO/FP):
Row Address Strobe (EDO/FP):
DRAM Row address strobe 5-0 for DRAM banks 2-0.
Chip Select (SDRAM) :
These pins activate the SDRAM and accept any command when
it is low.
DQM[7:0]#/
CAS[7:0]#
O
Pin Mask/Output Enable (SDRAM)/Column address strobe
(FPM/EDO) :
Column address strobe (FPM/EDO) :
DRAM Column address strobe 7-0 for byte 7-0.
Input / Output Data Mask (SDRAM) :
SDRAM output enables during a read cycle and a byte mask
during a write cycle.
WEA#
O
Memory Write A:
RAM Write is an active low output signal to enable local DRAM
writes.
Two copies are provided for loading purposes.
WEB#/MA14
O
Memory Write B / Memory Address line 14 :
RAM Write is an active low output signal to enable local DRAM
writes.
Two copies are provided for loading purposes.
This pin also can serve as MA14 signal by programming the
Register 52h bit4 to 1 to support the high density DRAM parts.
SRAS#
O
SDRAM Row Address Strobe :
It latches row address on the positive edge of the clock with
SRAS# low. These signals enable row access and precharge.
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