参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 40/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
131
Silicon Integrated Systems Corporation
Access:
RO
Register 02h
Bus Master Primary IDE Status Register
Default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7
RO
Simplex Only
This bit is hardwired to zero to indicate that both bus master channels can be
operated at a time.
6
R/W
Drive 1 DMA Capable
This R/W bit can be set by BIOS or driver to indicate that drive 1 for this
channel is capable of DMA transfers.
5
R/W
Drive 0 DMA Capable
This R/W bit can be set by BIOS or driver to indicate that drive 0 for this
channel is capable of DMA transfers.
4:3
RO
Reserved. Return 0 on reads
2
R/W
Interrupt
The bit is set by the rising edge of the IDE interrupt line to indicate that all data
transferred from the drive is visible in the system memory. Writing a '1' to this
bit can reset it.
1
RO
Error
This bit is set when the IDE controller encounters an error during data
transferring to/from memory.
0
R/W
Bus Master IDE Device Active
This bit is set when the start bit in the command register is set. It can be cleared
when the last transfer of a region is performed, or the start bit is reset.
Register 03h
Reserved
Default Value:
00h
Register 04h~07h
Bus Master Primary IDE PRD Table Pointer Register
This 32-bit register contains address pointing to the starting address of the PRD table.
Default Value:
00000000h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
31:2
R/W
Base Address of the PRD Table
1:0
R/W
Reserved
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