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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 74/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
32
Silicon Integrated Systems Corporation
5.2.3.
DRAM AUTO-DETECTION
SiS600 supports three banks DRAM for SIMM/DIMM from bank0 to bank2. The DRAM detection sequence is a
bank-based detection sequence, it is performed by the BIOS bank by bank and fulfilled the DRAM configuration
information into the corresponding DRAM configuration registers. The following steps will be described the
DRAM detection sequence.
Step 1.
To detect if there is any DRAM populated in bank N, SiS600 sets this bank with maximum DRAM
size, then writes/reads the same address with test pattern by the normal DRAM read/write timing and
compares the data. If the read data is the same as the write pattern, then there are exists DRAM in the
bank N; otherwise, proceeds the SDRAM detection from step 3.
Step 2.
If the DRAM is detected in the bank N by step 1, SiS600 treats it as EDO or FPM DRAM. SiS600
first writes test pattern into DRAM, then sets register 55h bit 6 (EDO Detection Bit) to be “1” in
HOST-to-PCI bridge configuration space, then reads the same DRAM location and compares with the
test pattern. The EDO detection bit will delay the data forward to CPU after 4096 CPU clock. If the
CPU still get the right data, then EDO mode DRAM is set to this row; otherwise, the FP mode
DRAM is set. Go to step 8.
Step 3.
If the DRAM is detected not populated in bank N by normal write/read procedure, SiS600 checks if
there is SDRAM existing in this bank or not. SiS600 first assumes the DRAM mode is SDRAM (set bit
[7:6] of register 60h/61h/62h to be “11” in HOST-to-PCI bridge configuration space, it depends on
which bank is under detection), and then does the SDRAM initialization procedure from step 4 to step 6.
Step 4.
Set register 57h bit 7 to be “1”, this bit will drive a precharge command to SDRAM, then disable this
bit (set to be “0”).
Step 5.
Set register 57h bit 6 to be “1”, this bit will drive a “Mode Register Set”(MRS) command to SDRAM.
When SDRAM receive MRS command, it will load the needed information (CAS Latency)
into
SDRAM. After doing MRS, disable this bit (set to be “0”).
Step 6.
Set register 57h bit 5 to be “1” at least two times, then SDRAM will perform refresh cycle at least two
times before the normal operation. Disable this bit (set to be “0”).
Step 7.
Write/Read the test pattern into SDRAM, then compare the data. If the data is correct, SDRAM is
detected, and set bank N as SDRAM; otherwise, bank N is no DRAM populated.
Step 8.
After DRAM mode is set, SiS600 does DRAM sizing by write/read test pattern based on the MA
mapping table.
Step 9.
Repeat from step 1 to step 8 to detect the other banks.
Note: The value of N is from 0 to 2.
The following will be shown the flow chart of DRAM Detection Sequence.
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