参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 121/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
75
Silicon Integrated Systems Corporation
3
R/W
SDRAM Write Retire Rate
This bit controls the timing that SiS600 writes data into SDRAM during burst cycles.
0: X-2-2-2
1: X-1-1-1
2
R/W
Precharge Command Timing Control.
This bit controls the timing for asserting precharge command when the address of the
next memory access cycle is located at different page than that of the current one.
0: One wait state
1: Zero wait state
1
R/W
SDRAM Multi-bank Function control
When enable, SiS600 supports SDRAM internal multi-bank function up to 4 banks.
0: Disable
1: Enable
0
R/W
NOP Command
When set, SiS600 will issue NOP command to SDRAM. This bit is automatically
cleared after the NOP command is completed.
0: Disable
1: Enable
Register 58h
EDO/FP DRAM CAS# Timing Control
default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7:6
R/W
CAS# Precharge Time for FP DRAM
Bits[7:6] Description
00
1T
01
1T during burst cycles, 2T for different cycles.
(One wait state between cycles)
10
2T
11
Reserved
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