参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 26/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
118
Silicon Integrated Systems Corporation
Register 06h
Status
Default Value:
0000h
Access:
Read/Write, Read Only, Write Clear
The Status register is used to record status information for PCI bus related events. Reads to this register behave
normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other
bits, write the value 0100_0000_0000_0000b to the register.
BIT
ACCESS
DESCRIPTION
15:14
RO
Reserved
These bits are hardware to zero.
13
WC
Master Abort Asserted
This bit is set when a PCI bus master IDE transaction is terminated by master
abort. While this bit is set, IDE will issue an interrupt request. This bit can be
cleared by writing a 1 to it.
12
WC
Received Target Abort
The bit is set whenever PCI bus master IDE transaction is terminated with
target abort.
11
RO
Signaled Target Abort
The bit will be asserted when IDE terminates a transaction with target abort.
11:9
RO
DEVSEL# Timing DEVT.
These two bits define the timing of asserting DEVSEL#. The built-in IDE
always asserts DEVSEL# in fast timing, and thus the two bits are hardwired to
0 per PCI Spec.
8
R/W
Reserved, Read as "0".
7:0
RO
Reserved
Default value is 00h
Register 08h
Revision ID
Default Value:
D0h
Access:
Read Only
BIT
ACCESS
DESCRIPTION
7:0
RO
Revision Identification Number
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