参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 119/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
73
Silicon Integrated Systems Corporation
Register 56h
DRAM MISC Control 3
default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7:4
R/W
MDLE Delay Control for EDO/FP Mode DRAM
These bits control the timing for internal latch signal MDLE, which is used to latch
MD after DRAM stops driving the MD line to guarantee DRAM masters will read
correct data from MD bus. The value of delay time depends on the specification
and the load of DRAM.
Bits[7:4] Delay
0000
0ns
0001
1ns
0010
2ns
0011
3ns
0100
4ns
0101
5ns
0110
6ns
0111
7ns
1000
8ns
1001
9ns
1010
10ns
1011
11ns
1100
12ns
1101
13ns
1110
14ns
1111
15ns
3
R/W
SDRAM Initialization Mode Selection
This bit controls whether the command specified in register 57h bits[7:5] should be
applied to one row only or to all rows. If this bit is 0, the DRAM Status Register
(Register 63h) will be to specify which row the command should be applied to.
0: One Row
1: All Rows
2
R/W
Reserved
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