参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 11/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
105
Silicon Integrated Systems Corporation
Register E0h
A.G.P. Compliant Target/Arbiter Control Register (ACTACR)
Default Value:
00h
Access:
Read/Write
The 8-bit register contains various options for A.G.P. compliant target and arbiter.
BIT
ACCESS
DESCRIPTION
7:6
R/W
Read Buffer Threshold Point for Read GNT
The read grant for low-priority AGP master will not be asserted on the A.G.P. bus
until certain threshold amount of data is available in the internal read buffer.
A.G.P. bus utilization will be improved if larger amount of data is transferred in a
single burst. Please note that high-priority read grant is not affected by this setting.
Bits[7:6]
Threshold
11
8 blocks
10
4 blocks
01
2 blocks
00
1 block
5
R/W
Pipeline Option for Read Grant
0: Fast
1: Slow
4
R/W
A.G.P. Flush Option
0: Flush only low priority write
1: Flush both high and low priority write
3
R/W
Assert GNT# in response to PIPE# or FRAME# without Holding CPU
When disabled, SiS600 can only asserts GNT# in response to A.G.P. master
requests by PIPE# or FRAME# when CPU is being held. When enabled, SiS600
may assert GNT# when CPU is not being held. This bit is recommended to set to 0
when a pure PCI device or an A.G.P. device using SBA is plugged in A.G.P. This
bit recommended to set to 1 when an A.G.P. device that will use PIPE# to its
requests is plugged in the system.
0: Disable
1: Enable
2
R/W
A.G.P. Counter Test Mode.
For internal test mode use only.
0: Normal Mode
1: Test Mode
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