参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 131/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
84
Silicon Integrated Systems Corporation
3:0
R/W
CKE Timing Control
These bits control the timing of CKE. When the value of this field is 0000, CKE is
driven out from flip-flop, otherwise, it is driven out from combinatorial logic.
Various delay options are provided to ensure that CKE can meet SDRAM setup time
and hold time specification when CKE is driven out from combinatorial logic.
Bits
Description
0000
Flip-flop Output
0001
Delay 2ns
0010
Delay 3ns
0011
Delay 4ns
0100
Delay 5ns
0101 Delay 6ns
0110 Delay 7ns
0111 Delay 8ns
1000 Delay 9ns
1001 Delay 10ns
1010 Delay 11ns
1011 Delay 12ns
1100 Delay 13ns
1101 Delay 14ns
1110 Delay 1ns
1111 No Delay
8.1.5. SHADOW RAM AREA
Register 70h~71h Shadow RAM Read Attribute Control
Default Value:
000000h
Access:
Read/Write
Register 70h and register 71h define the attribute of the Shadow RAM from 640 KByte to 1 MByte.
BIT
ACCESS
DESCRIPTION
15
R/W
Shadow RAM Enable for PCI Master Access
When enable, shadow RAM area can be accessed from PCI masters.
0: Disable
1: Enable
14:13
R/W
Reserved
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