参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 114/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
68
Silicon Integrated Systems Corporation
8.1.3.
DRAM CONTROL REGISTERS
Register 52h
DRAM MISC Control 1
default Value:
00h
Access:
Read/Write
The register defines timing for Refresh cycles.
BIT
ACCESS
DESCRIPTION
7
R/W
Test bit for DRAM Controller
0: Normal Mode
1: Test Mode
6:5
R/W
Reserved
4
R/W
Multi-function (Pin L1) for WEB#/MA14 Selection
0: WEB#
1: MA14
3
R/W
Reserved
2
R/W
SDRAM Refresh Command to Different ROW Control
When set to 0, refresh commands to different SDRAM rows initiated by SiS600
will be staggered one clock apart, such that the simultaneous-switching noise can
be reduced, i.e. CS[5:0]# will be asserted one after another. When set to 1, SiS600
will issue refresh commands to different SDRAM rows simultaneously.
0: Staggered one clock apart
1: Simultaneous
1
R/W
DRAM Refresh Test Mode
This bit is a test mode bit used for internal refresh circuit testing.
0: Normal Mode
1: Test Mode
0
R/W
CS# Behavior when SDRAM Refresh Cycles
This bit controls the behavior of CS# for SDRAM during refresh cycles. If there is
any SDRAM populated in the system, this bit should be programmed as 1.
0:Long pulse (CS# Behaves like RAS# during EDO/FP mode refresh cycles)
1:1T command pulse
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