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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 77/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
35
Silicon Integrated Systems Corporation
INITIALIZATION
When ECC is enabled, the whole DRAM modules must be first initialized by doing writes before the DRAM read
operations to establish the correlation between 64-bit data and associated 8-bit ECC code which does not exist
after power-on.
ECC DETECTION AND CORRECTION
During DRAM read operations, the full Qword of data and the associated ECC code are transferred
simultaneously from DRAM to the SiS600. If there is a single-bit error in the 72-bit signals (64-bit data plus 8-bit
code), the ECC mechanism will automatically recover the correct 64-bit data. Note that the recovered data is
transferred to the requesting master (Host, PCI, or AGP interface), but the DRAM controller does not initiate a
DRAM write cycle to fix the single-bit error in DRAM.
If the ECC mechanism detects a two-bit error, SiS600 can report this error by SERR# or record it on the Error
Status Register optionally.
ECC GENERATION
During DRAM write operations, SiS600 automatically generates an 8-bit ECC code for the 64-bit data. If the
requested write operation transfers single or multiple Qword of data, the ECC DRAM write can be completed
without any overhead. If the write request only transfers less than 64 bits of data, the DRAM controller performs
a read-merge-write operation.
5.3.
PCI BRIDGE
The PCI bridge of SiS600 consists of three parts: PCI arbiter, PCI master bridge and PCI target bridge. The PCI
arbiter controls the assignment of PCI bus ownership among all PCI masters. The PCI master bridge forwards the
transactions from host bus. The PCI target bridge claims PCI cycles toward system memory or AGP bus as
required by PCI master devices.
5.3.1.
PCI ARBITER
The main function of PCI arbiter takes charge of the PCI bus ownership assignment. This PCI arbiter supports at
most 4 external PCI masters using standard PCI REQ#/GNT# mechanism and 1 PCI master using
PHOLD#/PHLDA# mechanism. The master that uses PHOLD#/PHLDA mechanism is not pre-emptive. That
means the master can own the bus as long as it wishes after it gains the control of PCI bus. The master that use
PHOLD#/PHLDA# mechanism to access PCI bus is typically SiS5595 chip.
Arbitration Algorithm
PCI Masters (Agent 0~6, SIO) Requests
Figure6.4-1 Arbitration Tree shows the arbitration tree in arbiter design. Whenever a PCI cycle occurs, priority
status will be changed. The initial priority for master 0-7 to own PCI bus is 4 -> 0->SIO->2->5->1->6->3->4...
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相关代理商/技术参数 |
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| SIS776DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:N-Channel 30 V (D-S) MOSFET with Schottky Diode |
| SIS776DN-T1-GE3 | 制造商:Vishay Siliconix 功能描述:MOSFET N-CH 30V 18.3A 1212-8 |
| SiS778DN-T1-GE3 | 功能描述:MOSFET 30 Volts 35 Amps 52 Watts RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SIS780DN | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:N-Channel 30 V (D-S) MOSFET with Schottky Diode |
| SiS780DN-T1-GE3 | 功能描述:MOSFET 30 Volts 18 Amps 27.7 Watts RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
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