参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 29/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
121
Silicon Integrated Systems Corporation
In the native mode, above four registers define the IDE base address for each of the two IDE devices in both the
primary and secondary channels respectively. In the compatible mode, the four registers can still be programmed
and read out, but it does not affect the IDE address decoding.
Register 20h~23h Bus Master IDE Control Register Base Address
OFFSET REGISTER
REGISTER ACCESS
00H
Bus Master IDE Command Register (Primary)
01H
Reserved
02H
Bus Master IDE Status Register(Primary)
03H
Reserved
04-07H
Bus Master IDE PRD (*) Table Pointer (Primary)
08H
Bus Master IDE Command Register (Secondary)
09H
Reserved
0AH
Bus Master IDE Status Register (Secondary)
0BH
Reserved
0C-0FH
Bus Master IDE PRD (*) Table Pointer (Secondary)
*PRD: Physical Region Descriptor
Register 24h~2Bh Reserved
Default Value:
00h
Access:
RO
Register 2C~2Dh
Subsystem Vendor ID
Default Value:
0000h
Access:
Read/Write
This register can be written once and is used to identify vendor of the subsystem.
Register 2Eh~2Fh Subsystem Vendor ID
Default Value:
0000h
Access:
Read/Write
This register can be written once and is used to identify subsystem ID.
Register 30h~33h Expansion ROM Base Address
Default Value:
00000000h
Access:
Read/Write
Register 34h~3Fh Reserved
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