参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 27/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
119
Silicon Integrated Systems Corporation
Register 09h
Programming Interface
Default Value:
00h
Access:
Read Only
The default value is 00h since no specific register-level programming interface is provided.
BIT
ACCESS
DESCRIPTION
7
RO
Master IDE Device
This bit is hardwired to one to indicate that the built-in IDE is capable of
supporting bus master function.
6:4
RO
Reserved
3
RO
Secondary IDE Programmable Indicator
When the bit is programmed as "1", it means that the primary channel can be
programmed to operate in compatible or native mode. When the bit is
programmed as "0"the mode is fixed and is determined by the value of bit 2.
This bit should be programmed as
1
during the BIOS boot up procedures.
2
RO
Secondary IDE Operating Mode
This bit defines the mode that the secondary IDE channel is operating in. Zero
corresponds to 'compatibility' while one means native mode. By default, this
bit is 0 and is programmable.
1
RO
Primary IDE Programmable Indicator
When the bit is programmed as '1', it means that the primary channel can be
programmed to operate in compatible or native mode. When the bit is
programmed as
0
, the mode is fixed and is determined by the value of bit
0. This bit should be programmed as
1
during the BIOS boot up
procedures.
0
RO
Primary IDE Operating Mode
This bit defines the mode that the primary IDE channel is operating in. Zero
corresponds to 'compatibility' while one means native mode. By default, this
bit is 0 and is programmable.
Register 0Ah
Sub Class Code
Default Value:
01h
Access:
Read Only
BIT
ACCESS
DESCRIPTION
7:0
RO
Sub Class Code
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