参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 142/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
94
Silicon Integrated Systems Corporation
Register 84~85h
PCI 33/66 Grant Timer
Default Value:
FFFFh
Access:
Read/Write
The timer is used to prevent PCI masters from seizing the PCI bus too long. When the timer expires, PCI arbiter
forces the master that is currently occupying PCI bus to relinquish PCI bus by removing its grant.
BIT
ACCESS
DESCRIPTION
15:0
R/W
PCI 33/66 Grant Timer
The setting of this register and MLT (register 1Dh) should be determined from the
perspective of overall system performance. For a system with many PCI master
devices, the value should be higher. For a system with fewer master devices, the
value should be smaller. Typical value of this timer is 60h if MLT is set to 20h.
Unit: PCI clock
Register 86h
CPU Idle Timer for PCI
Default Value:
FFh
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7:0
R/W
CPU Idle Timer
Recommended value for this timer is 03h.
Unit: PCI clock
Register 87h
General Purpose Register I
Default Value:
00h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
7:0
R/W
General Purpose Register
This register provides the storage information for BIOS programming.
Register88h~89h Base address of fast back-to-back area
Default Value:
0000h
Access:
Read/Write
PCI cycles fall within this area will be carried out with fast back-to-back cycles, provided PCI spec is not violated.
BIT
ACCESS
DESCRIPTION
15:4
R/W
Frame Buffer Base Address
Bits[15:4] correspond to A[31:20] of the base address. The frame buffer base
address must be 1MByte aligned.
3:0
R/W
Reserved
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