参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 23/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
116
Silicon Integrated Systems Corporation
3
R/W
VGA Enable
The bit controls the forwarding of transactions initiated by CPU. When the bit is
enabled, 600 forwards CPU-initiated cycles with the following address to A.G.P.
bus.
Memory Address: 0A0000h ~ 0BFFFFh
I/O Address: 3B0h ~ 3BBh, 3C0 ~ 3DFh
0 : Disable
1 : Enable
2
R/W
ISA Enable
When enable, I/O cycles with addresses fall within the upper 768 bytes in each
1KB block (i.e., A9 or A8 = 1) will be forwarded to Primary PCI even if the
address is within the range defined by the IOBASE and IOLIMIT.
0 : Disable
1 : Enable
1
R/W
System Error Enable
This bit and bit 1 of the bridge control register (offset 3Fh) control the forwarding
of ASERR# on A.G.P. to SERR# on PCI bus. When both of these two bits are
enabled, SiS600 asserts SERR# when it detects the assertion of ASERR# on A.G.P.
When any one of these two bits is disabled, the assertion of ASERR# won’t affect
SERR#.
0: Disable
1: Enable
0
RO
Reserved
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