参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 111/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
66
Silicon Integrated Systems Corporation
0
R/W
PCI 33/PCI 66 Masters Concurrently Access Memory Function
When enabled, PCI33 and PCI66 masters requesting for memory access cycles will
be granted simultaneously, such that their memory access cycle can be optimized.
When disabled, only one of PCI33 and PCI66 masters can be granted. In case their
requests are asserted at the same time, PCI66 masters have higher priority than
PCI33.
0: Disabled
1: Enabled
Register 51h
Host Bus Interface control II
default Value:
02h
Access:
Read/Write
BIT
ACCESS
DESCRIPTION
5
R/W
Support Asynchronous Clock Mode between Host and PCI clock
0: Disable
1: Enable
4
R/W
Reserved
3
R/W
Host to PCI33/66 concurrency Control
0: Enable
1: Disable
2
R/W
Host-to-SDRAM Pipelined Read Timing Control
When set to 1, there will be no wait state between SDRAM back-to-back read
cycles; when set to 0, there will be one wait state inserted in between.
0: x-1-1-1-2-1-1-1.....
1: x-1-1-1-1-1-1-1.....
1
R/W
Host-to-PCI Cycle Timing Control
When set to 1, the Host-to-PCI bridge will start the translation of Host-to-PCI
cycle once the cycle appears on the host bus. When set to 0, the start of the Host-
to-PCI translation will be delayed by one CPU clock.
0: Delay 1 CPU clock
1: Without Delay
7:6
R/W
Reserved
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