SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
iii
Silicon Integrated Systems Corporation
FIGURE
FIGURE 2.2-1 FUNCTIONAL BLOCK DIAGRAM....................................................................................................5
FIGURE 3.1-1 SiS600 PIN ASSIGNMENT (TOP VIEW-LEFT SIDE).....................................................................6
FIGURE 3.1-2 SiS600 PIN ASSIGNMENT (TOP VIEW-RIGHT SIDE)...................................................................7
FIGURE 5.1-1 BLOCK DIAGRAM FOR HOST INTERFACE...................................................................................24
FIGURE 5.2-1 EDO/FPM DRAM CONFIGURATION .......................................................................................25
FIGURE 5.2-2 SDRAM CONFIGURATION ..........................................................................................................26
FIGURE 5.2-3 MIXED DRAM CONFIGURATION ...............................................................................................26
FIGURE 5.2-4 DRAM DETECTION SEQUENCE..................................................................................................33
FIGURE 5.2-5 GRAPHIC ADDRESS RE-MAPPING FUNCTION ............................................................................34
FIGURE 5.3-1 ARBITRATION TREE......................................................................................................................36
FIGURE 5.3-2 BLOCK DIAGRAM FOR PMR ........................................................................................................38
FIGURE 5.3-3 LINE READ CYCLE........................................................................................................................39
FIGURE 5.3-4 NON-POST CYCLE.........................................................................................................................40
FIGURE 5.3-5 POST WRITE AND BURST CYCLE.................................................................................................40
FIGURE 5.3-6 BLOCK DIAGRAM OF 66MHZ PCI MASTER BRIDGE ................................................................41
FIGURE 5.4-1 BLOCK DIAGRAM OF AGP COMPLIANT TARGET/HOST-TO-PCI66 BRIDGE........................42
FIGURE 5.6-1 BLOCK DIAGRAM FOR IDE CONTROLLER ...............................................................................43
FIGURE 5.7-1 THE MECHANISM OF NAND TREE.............................................................................................49
FIGURE 5.7-2 THE TEST SCHEME OF NAND TREE..........................................................................................50
FIGURE 10-1 MECHANICAL DIMENSION ......................................................................................................... 138
FIGURE 10-2 600 BALL ASSIGNMENT ............................................................................................................. 139
TABLE
TABLE 5.6-1 ACCESSING METHOD TO I/O PORTS FOR PRIMARY CHANNEL ................................................44
TABLE 5.6-2 ACCESSING METHOD TO I/O PORTS FOR SECONDARY CHANNEL...........................................45
TABLE 5.6-3 TABLE FOR DIFFERENT COMMAND DEFINITION........................................................................47
TABLE 5.7-1 NAND TREE LIST FOR SIS600 .....................................................................................................50
TABLE 9.1-1 ABSOLUTE MAXIMUM RATINGS................................................................................................ 134
TABLE 9.2-1 DC CHARACTERISTICS OF HOST, DRAM, PCI AND IDE INTERFACE............................... 134
TABLE 9.2-2 DC CHARACTERISTICS OF A.G.P. INTERFACE........................................................................ 135