参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 85/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
42
Silicon Integrated Systems Corporation
When PSL66 is processing accesses toward system DRAM, it checks whether the CPU is held or not. If the CPU
is not held, PSL66 generates hold request to host interface. Host interface responds to this hold signal by asserting
HLDA66. After the HLDA is returned, PSL66 has totally control over the host bus and then the accesses can be
continued.
PSL66 and PMR66 share the same FIFO (CTAFF and ATHFF). The usage of the shared FIFO is mutual
exclusive. PSL66’s operation toward system memory will be suspended until all PMR66’s data are flushed out of
CTAFF.
In general, the functions of PSL66 are the same with the ones of PSL33. For further details of functional
descriptions, make reference to the paragraph of PSL33.
5.4.
A.G.P. COMPLIANT TARGET/HOST-TO-PCI66 BRIDGE
A.G.P. Compliant Target/Host-to-PCI66 Bridge is constituted by 4 blocks: A.G.P. arbiter, A.G.P. Target, PMR66
and PSL66. The A.G.P. arbiter coordinates the operation of A.G.P. Target, PMR66 and A.G.P. compliant master.
The A.G.P. target is response for transferring data between A.G.P. bus and dram controller when the A.G.P.
compliant target initiate bus transactions with A.G.P. protocol. PMR66 forward cycles from host bus or 33Mhz
PCI bus to A.G.P. bus with PCI protocol. PSL66 claims PCI transactions which are destining to system memory.
DRAM
A.G.P.
Port
Host Bus
PSL66
AGP
Target
AGP
Arbiter
PMR66
PSL33
PCI
Bus
control
data
Dram
Controller
&
Dram
Arbiter
Figure 5.4-1 Block Diagram of AGP Compliant Target/Host-to-PCI66 Bridge
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