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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 89/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
46
Silicon Integrated Systems Corporation
enabled, the write IDE data port command on PCI bus will last for 3 PCI clocks only. When disabled, the PCI
command will be 5 PCI clocks.
DMA mode operation
There is a DMA engine associated with each channel. The DMA engine can be invoked by writing the start-bit in
Bus Master command register. The DMA engine will first request for PCI bus to read the descriptor from
memory, load the address pointer and byte-count. For IDE read operation, the controller will start prefetching
data into FIFO at this moment. When FIFO is half-full (or 75% full, programmable), the DMA engine will
request for PCI bus to flush the data in FIFO to memory. If the prefetch count is reached while the FIFO is not yet
half-full, the DMA engine will also request for PCI bus to flush the FIFO. For write operation, after descriptor is
read, the DMA engine will again request for PCI bus to read data from memory to FIFO. At the same time, when
the FIFO becomes non-empty, the controller will automatically start IDE write cycles to flush data in FIFO to
IDE device. When data in FIFO is less than eight bytes, the DMA engine will again request for PCI bus to re-fill
the FIFO.
Normally, the byte-count loaded in IDE controller will be equal to IDE transfer size programmed to
IDE devices. If the two values were programmed differently, the IDE controller and the software that
driving IDE should work together to prevent system from failure.
When the DMA engine is writing IDE
If the byte-count was programmed to be greater than the IDE transfer size, the IDE device will de-assert IDREQ
signal when the transfer size is reached and issues interrupt to IDE controller. The IDE controller will pass
transparently the interrupt to host. When the host clears the start-bit in response to the interrupt, the IDE
controller will simply discard the remaining data in FIFO. When the host reads the status bit, it will see the
interrupt bit set and active bit also set. This will be interpreted as a normal ending. If the byte-count was
programmed to be less than the IDE transfer size, the controller will exhaust its data in FIFO while IDREQ signal
is still asserting. The host should time-out because it does not receive any interrupt. When the host reads the
status register, it will see the interrupt bit not set and the active bit set.
When the DMA engine is reading IDE
If the byte-count was programmed to be greater than the IDE transfer size, the IDE device will de-assert IDREQ
signal when the transfer size is reached and issue interrupt to IDE controller. The IDE controller should mask the
interrupt, request for PCI bus to flush all the data in FIFO to memory. After the FIFO is empty, the controller will
unmask the interrupt to inform host that all data is visible in memory. The host, after receiving the interrupt, will
read the status register and see the interrupt bit set and active bit also set. This will be interpreted as a normal
ending.
If the byte count was programmed to be less than the IDE transfer size, the IDE controller will stop prefetching
when its byte-count has reached while IDREQ signal is still asserted by device. The controller may or may not
flush its data in FIFO to memory, depending on whether the FIFO has reached its request level or not. The host
will eventually be time-out because it does not receive any interrupt. When the host reads the status register, it
will see the interrupt bit not set and the active bit set. The remaining data in FIFO will be discarded when the host
clears the start-bit.
Ultra-DMA/33 Operation
Ultra DMA is a fast data transfer protocol used on IDE bus. By utilizing both the rising edge and the falling edge
of the data strobe signal to latch data from DD[15:0], the data transfer rate is effectively doubled than that of the
traditional multi-word DMA while the highest fundamental frequency on the cable is the same. In view of the
faster transfer rate on IDE bus may easily fill the FIFO up when reading IDE device, in such condition the IDE
bus will be idle and result in system performance degradation, SiS Chip lengthens the internal FIFO for each
channel (channel 0/channel 1) to 16-Dword to improve system performance. When the FIFO is half-full (or 3/4-
full, programmable), the DMA engine should request for PCI bus by asserting an internal request signal to system
arbiter. The system arbiter, based on an algorithm described in the previous sections, shall grant the PCI bus to
DMA engine by asserting an internal grant signal to it. Ideally, the FIFO should never be full during data-in
operation so that the burst data transfers on IDE will not be suspended. When the IDE controller is transferring
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